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| d a t a sh eet product speci?cation supersedes data of 1995 dec 06 file under integrated circuits, ic01 1998 feb 26 integrated circuits SAA7374 low voltage digital servo processor and compact disc decoder (cd7lv)
1998 feb 26 2 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 contents 1 features 2 general description 3 quick reference data 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 decoder part 7.1.1 principle operational modes of the decoder 7.1.2 decoding speed and crystal frequency 7.1.3 lock-to-disc mode 7.1.4 standby modes 7.2 crystal oscillator 7.3 data slicer and clock regenerator 7.4 demodulator 7.4.1 frame sync protection 7.4.2 efm demodulation SAA7374 7.5 subcode data processing 7.5.1 q-channel processing 7.5.2 eiaj 3 and 4-wire subcode (cd graphics) interface 7.5.3 v4 subcode interface 7.6 fifo error corrector 7.6.1 flags output (cflg) 7.6.2 c2fail 7.7 audio functions 7.7.1 de-emphasis and phase linearity 7.7.2 digital oversampling filter 7.7.3 concealment 7.7.4 mute, full-speed, attenuation and fade 7.7.5 peak detector 7.8 dac interface 7.9 ebu interface 7.9.1 format 7.10 kill circuit 7.11 audio features off 7.12 the via interface 7.13 spindle motor control 7.13.1 motor output modes 7.13.2 spindle motor operating modes 7.13.3 loop characteristics 7.13.4 fifo overflow 7.14 servo part 7.14.1 diode signal processing 7.14.2 signal conditioning 7.14.3 focus servo system 7.14.4 radial servo system 7.14.5 off-track counting 7.14.6 defect detection 7.14.7 off-track detection 7.14.8 high level features 7.14.9 driver interface 7.14.10 laser interface 7.14.11 radial shock detector 7.15 microcontroller interface 7.15.1 microcontroller interface (4-wire bus mode) 7.15.2 microcontroller interface (i 2 c-bus mode) 7.15.3 summary of functions controlled by registers 0tof 7.15.4 summary of servo commands 7.15.5 summary of servo command parameters 8 limiting values 9 operating characteristics 10 operating characteristics (subcode interface timing) 11 operating characteristics (i 2 s-bus timing) 12 operating characteristics (microcontroller interface timing) 13 application information 14 package outline 15 soldering 15.1 introduction 15.2 reflow soldering 15.3 wave soldering 15.4 repairing soldered joints 16 definitions 17 life support applications 18 purchase of philips i 2 c components 1998 feb 26 3 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 1 features cd-rom mode single and double-speed modes lock-to-disc mode full error correction strategy, t = 2 and e = 4 full cd graphics interface all standard decoder functions implemented digitally on chip fifo overflow concealment for rotational shock resistance digital audio interface (ebu), audio and data 2 and 4 times oversampling integrated digital filter, including f s mode audio data peak level detection kill interface for dac deactivation during digital silence all tda1301 (dsic2) digital servo functions, plus extra high-level functions low focus noise improved playability on abex tcd-721r, tcd-725 and tcd-714 discs automatic closed loop gain control available for focus and radial loops pulsed sledge support microcontroller loading low high-level servo control option high-level mechanism monitor communication may be via tda1301/saa7345 compatible bus or i 2 c-bus on-chip clock multiplier allows the use of 8.4672 mhz crystal. 2 general description the SAA7374 (cd7lv) is a low-voltage chip which combines the functions of a cd decoder ic and digital servo ic. the decoder part is based on the saa7345 (cd6) with an improved error correction strategy. the servo part is based on the tda1301t (dsic2) with improvements incorporated. extra features have also been added. supply of this compact disc ic does not convey an implied license under any patent right to use this ic in any compact disc application. 3 quick reference data 4 ordering information symbol parameter conditions min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v i dd supply current n = 1 mode - 28 - ma f xtal crystal frequency 8 8.4672 35 mhz t amb operating ambient temperature - 10 - +70 c t stg storage temperature - 55 - +125 c type number package name description version SAA7374gp qfp64 plastic quad ?at package; 64 leads (lead length 1.6 mm); body 14 14 2.7 mm sot393-1 1998 feb 26 4 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 5 block diagram fig.1 block diagram. handbook, full pagewidth decoder micro- controller interface versatile pins interface subcode processor kill peak detect serial data interface timing test adc v ref generator front end digital pll motor control audio processor ebu interface error corrector microcontroller interface pre- processing control function control part efm demodulator sram ram addresser output stages flags 6 8 9 11 52 51 53 54 15 17 14 18 20 23 29 13 21 22 24 25 50 35 36 38 37 58 57 62 63 42 41 40 43 3 4 5 7 10 1 12 16 2 19 32 39 49 56 30 47 59 26 27 28 64 33 34 61 60 31 48 46 45 44 v rl v rh i ref r2 scl sda rab sild hfin hfref islice test1 test2 test3 selpll crin crout cl16 cl11 cl4 sbsy sfsy sub rck status reset r1 d1 d2 d3 d4 i reft v ssa1 v ssa3 v dda2 v ssd2 v ssd4 v ddd2(p) v ssa2 v dda1 v ssd1 v ssd3 v ddd1(p) v ddd3(c) v1 v2 v3 v4 v5 kill ef data wclk sclk dobm c2fail moto2 moto1 ldon sl fo ra cflg SAA7374 mbg648 1998 feb 26 5 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 6 pinning symbol pin description v ssa1 1 (1) analog ground 1 v dda1 2 (1) analog supply voltage 1 d1 3 unipolar current input (central diode signal input) d2 4 unipolar current input (central diode signal input) d3 5 unipolar current input (central diode signal input) v rl 6 reference voltage input for adc d4 7 unipolar current input (central diode signal input) r1 8 unipolar current input (satellite diode signal input) r2 9 unipolar current input (satellite diode signal input) i reft 10 current reference output for adc calibration v rh 11 reference voltage output from adc v ssa2 12 (1) analog ground 2 selpll 13 selects whether internal clock multiplier pll is used islice 14 current feedback output from data slicer hfin 15 comparator signal input v ssa3 16 (1) analog ground 3 hfref 17 comparator common mode input i ref 18 reference current output pin (nominally 0.5v dd ) v dda2 19 (1) analog supply voltage 2 test1 20 test control input 1; this pin should be tied low crin 21 crystal/resonator input crout 22 crystal/resonator output test2 23 test control input 2; this pin should be tied low cl16 24 16.9344 mhz system clock output cl11 25 11.2896 or 5.6448mhz clock output (3-state) ra 26 radial actuator output fo 27 focus actuator output sl 28 sledge control output test3 29 test control input 3; this pin should be tied low v ddd1(p) 30 (1) digital supply voltage 1 for periphery dobm 31 bi-phase mark output (externally buffered; 3-state) v ssd1 32 (1) digital ground 1 moto1 33 motor output 1; versatile (3-state) moto2 34 motor output 2; versatile (3-state) sbsy 35 subcode block sync output (3-state) sfsy 36 subcode frame sync output (3-state) rck 37 subcode clock input sub 38 p-to-w subcode bits output (3-state) v ssd2 39 (1) digital ground 2 v5 40 versatile output pin 5 1998 feb 26 6 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 note 1. all supply pins must be connected to the same external power supply voltage. v4 41 versatile output pin 4 v3 42 versatile output pin 3 (open-drain) kill 43 kill output (programmable; open-drain) ef 44 c2 error ?ag; output only de?ned in cd rom and 1f s modes (3-state) data 45 serial data output (3-state) wclk 46 word clock output (3-state) v ddd2(p) 47 (1) digital supply voltage 2 for periphery sclk 48 serial bit clock output (3-state) v ssd3 49 (1) digital ground 3 cl4 50 4.2336 mhz microcontroller clock output sda 51 microcontroller interface data i/o line (open-drain output) scl 52 microcontroller interface clock line input rab 53 microcontroller interface r/ w and load control line input (4-wire bus mode) sild 54 microcontroller interface r/w and load control line input (4-wire-bus mode) n.c. 55 not connected v ssd4 56 (1) digital ground 4 reset 57 power-on reset input (active low) status 58 servo interrupt request line/decoder status register output (open-drain) v ddd3(c) 59 (1) digital supply voltage 3 for core c2fail 60 indication of correction failure output (open-drain) cflg 61 correction ?ag output (open-drain) v1 62 versatile input pin 1 v2 63 versatile input pin 2 ldon 64 laser drive on output (open-drain) symbol pin description 1998 feb 26 7 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 fig.2 pin configuration. handbook, full pagewidth SAA7374 mbg646 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v ssa1 v dda1 d1 d2 d3 v rl d4 r1 r2 i reft v rh v ssa2 selpll islice hfin v ssa3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 sclk v ddd2(p) wclk data ef kill v3 v4 v5 v ssd2 sub rck sfsy sbsy moto2 moto1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 hfref i ref v dda2 test1 crin crout test2 cl16 cl11 ra fo sl test3 v ddd1(p) dobm v ssd1 ldon v2 v1 cflg c2fail v ddd3(c) status reset v ssd4 n.c. sild rab scl sda cl4 v ssd3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1998 feb 26 8 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 7 functional description 7.1 decoder part 7.1.1 p rinciple operational modes of the decoder the decoding part can operate at different disc speeds, from single-speed (n = 1) up to double-speed (n = 2). the factor n is called the overspeed factor. a simplified data flow through the decoder part is illustrated in fig.6. 7.1.2 d ecoding speed and crystal frequency the SAA7374 is a multi-speed decoding device, with an internal phase-locked loop (pll) clock multiplier. depending on the crystal frequency used and the internal clock settings (selectable via register b), the playback speeds shown in table 1 are possible, where n is the overspeed factor. an internal clock multiplier is present, controlled by selpll, and should only be used if an 8.4672 mhz crystal, ceramic resonator or external clock is present. 7.1.3 l ock - to - disc mode for high speed cd-rom applications, the SAA7374 has a special mode, the lock-to-disc mode. this allows constant angular velocity (cav) disc playback with varying input data rates from the inside-to-outside of the disc. in the lock-to-disc mode, the fifo is blocked and the decoder will adjust its output data rate to the disc speed. hence, the frequency of the i 2 s-bus (wclk and sclk) clocks are dependent on the disc speed. in the lock-to-disc mode there is a limit on the maximum variation in disc speed that the SAA7374 will follow. disc speeds must always be within 25 to 100% range of their nominal value. the lock-to-disc mode is enabled/disabled by register e. 7.1.4 s tandby modes the SAA7374 may be placed in two standby modes selected by register b (it should be noted that the device core is still active) standby 1: cd-stop mode. most i/o functions are switched off. standby 2: cd-pause mode. audio output features are switched off, but the motor loop, the motor output and the subcode interfaces remain active. this is also called a hot pause. in the standby modes the various pins will have the following values; moto1 and moto2: put in high-impedance, pwm mode (standby 1 and reset, operating in standby 2). put in high-impedance, pdm mode (standby 1 and reset, operating in standby 2). scl, sda, sild and rab: no interaction. normal operation continues. sclk, wclk, data, ef, cl11 and dobm: 3-state in both standby modes. normal operation continues after reset. crin, crout, cl16 and cl4: no interaction. normal operation continues. v1, v2, v3, v4, v5, cflg and c2fail: no interaction. normal operation continues. table 1 playback speeds note 1. the cl11 output is always a 5.6448 mhz clock if a 16.9344 mhz external clock is used. register b selpll crystal frequency (mhz) cl11 frequency (mhz) (1) 33.8688 16.9344 8.4672 00xx 0 n = 1 -- 11.2896 00xx 1 -- n = 1 11.2896 01xx 0 - n=1 - 5.6448 10xx 0 n = 2 -- 11.2896 10xx 1 -- n = 2 11.2896 11xx 0 - n=2 - 5.6448 1998 feb 26 9 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 7.2 crystal oscillator the crystal oscillator is a conventional 2 pin design operating between 8 and 35 mhz. this oscillator is capable of operating with ceramic resonators as well as with both fundamental and third overtone crystals. external components should be used to suppress the fundamental output of the third overtone crystals as shown in figs 3 and 4. typical oscillation frequencies required are 8.4672, 16.9344 or 33.8688 mhz depending on the internal clock settings used and whether or not the clock multiplier is enabled. fig.3 8.4672 mhz fundamental configuration. 8.4672 mhz crin crout SAA7374 22 pf 22 pf 330 w 100 k w oscillator mbg650 fig.4 33.8688 mhz overtone configuration. oscillator 33.8688 mhz crin crout SAA7374 3.3 m h 1 nf 10 pf 10 pf 330 w 100 k w mbg658 7.3 data slicer and clock regenerator the SAA7374 has an integrated slice level comparator which can be clocked by the crystal frequency clock, or 8 times the crystal frequency clock (if selpll is set high while using an 8.4672 mhz crystal, and register 4 is set to 0xxx). the slice level is controlled by an internal current source applied to an external capacitor under the control of the digital phase-locked loop (dpll). regeneration of the bit clock is achieved with an internal fully digital pll. no external components are required and the bit clock is not output. the pll has two registers (8 and 9) for selecting bandwidth and equalization. for certain applications an off-track input is necessary. this is internally connected from the servo part (its polarity can be changed by the foc_parm1 parameter), but may be input via the v1 pin if selected by register c. if this flag is high, the SAA7374 will assume that its servo part is following on the wrong track, and will flag all incoming hf data as incorrect. 1998 feb 26 10 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 fig.5 data slicer showing typical application components (for n = 1). handbook, full pagewidth 47 pf 22 nf 2.2 k w hfin hfref i ref islice 22 k w 150 k w 100 nf 2.2 nf hf input crystal clock dq dpll 1/2v dd v ssa v ssa v ss v ssa mbg649 v dd 100 m a 100 m a 7.4 demodulator 7.4.1 f rame sync protection a double timing system is used to protect the demodulator from erroneous sync patterns in the serial data. the master counter is only reset if; a sync coincidence detected; sync pattern occurs 588 1 efm clocks after the previous sync pattern. a new sync pattern is detected within 6 efm clocks of its expected position. the sync coincidence signal is also used to generate the pll lock signal, which is active high after 1 sync coincidence found, and reset low if during 61 consecutive frames no sync coincidence is found. the pll lock signal can be accessed via the sda or status pins selected by register 2 and 7. also incorporated in the demodulator is a rl2 (run length 2) correction circuit. every symbol detected as rl2 will be pushed back to rl3. to do this the phase error of both edges of the rl2 symbol are compared and the correction is executed at the side with the highest error probability. 7.4.2 efm demodulation the 14-bit efm data and subcode words are decoded into 8-bit symbols. 1998 feb 26 11 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth subcode processor digital pll and demodulator fifo error corrector fade/mute/ interpolate digital filter phase compensation de-emphasis filter kill 1 0 1 0 1 0 1 0 1 0 i 2 s-bus interface sclk wclk data ef reg 3 reg c reg 3 reg f reg a 1 0 1 : reg 3 1 101x 0 : reg 3 = 101x 0 : reg d = xx01 0 : reg a = xx1x 1 : reg a = xx0x (cd-rom modes) v4 subcode interface microcontroller interface cd graphics interface ebu interface sbsy sfsy sub dobm v4 sda output from data slicer 1 : reg 3 = xx10 (1f s mode) 0 : reg 3 1 xx10 1 : no pre-emphasis detected or reg d = 01xx (de-emphasis signal at v5) 0 : pre-emphasis detected and reg d 1 01xx kill v3 mbg418 fig.6 simplified data flow of decoder functions. 1998 feb 26 12 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 7.5 subcode data processing 7.5.1 q- channel processing the 96-bit q-channel word is accumulated in an internal buffer. the last 16 bits are used internally to perform a cyclic redundancy check (crc). if the data is good, the subqready-i signal will go low. subqready-i can be read via the sda or status pins, selected via register 2. good q-channel data may be read from sda. 7.5.2 eiaj 3 and 4- wire subcode (cd graphics ) interface data from all the subcode channels (p-to- w) may be read via the subcode interface, which conforms to eiaj cp-2401. the interface is enabled and configured as either a 3-wire or 4-wire interface via register f. the subcode interface output formats are illustrated in fig.7, where the rck signal is supplied by another device such as a cd graphics decoder. 7.5.3 v4 subcode interface data of subcode channels, q-to-w, may be read via pin v4 if selected via register d. the format is similar to rs232 and is illustrated in fig.8. the subcode sync word is formed by a pause of (200/n) m s minimum. each subcode byte starts with a logic 1 followed by 7 bits (q-to-w). the gap between bytes is variable between (11.3/n) m s and (90/n) m s. the subcode data is also available in the ebu output (dobm) in a similar format. fig.7 eiaj subcode (cd graphics) interface format. handbook, full pagewidth sbsy sfsy rck sub sfsy rck sub sfsy rck sub eiaj 4-wire subcode interface eiaj 3-wire subcode interface sf0 sf1 sf2 sf3 sf97 sf0 sf1 p-w p-w p-w p-w p-w p-w pqrstuvw mbg410 sf0 sf1 sf2 sf3 sf97 sf0 sf1 1998 feb 26 13 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 fig.8 subcode format and timing on pin v4. n = disc speed w96 1qrstuvw 1q 200/n m s min 11.3/n m s 11.3/n m s min 90/n m s max mbg401 7.6 fifo and error corrector the SAA7374 has a 8 frame fifo. the error corrector is a t = 2, e = 4 type, with error corrections on both c1 (32 symbol) and c2 (28 symbol) frames. four symbols are used from each frame as parity symbols. this error corrector can correct up to two errors on the c1 level and up to four errors on the c2 level. the error corrector also contains a flag processor. flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good. c1 generates output flags which are read after (de-interleaving) by c2, to help in the generation of c2 output flags. the c2 output flags are used by the interpolator for concealment of uncorrectable errors. they are also output via the ebu signal (dobm) and the ef output with i 2 s-bus for cd-rom applications. 7.6.1 f lags output (cflg) the flags output pin cflg (open-drain) shows the status of the error corrector and interpolator and is updated every frame (7.35 n khz). in the SAA7374 chip a 1-bit flag is present on the cflg pin as illustrated in fig.9. this signal shows the status of the error corrector and interpolator. the first flag bit, f1, is the absolute time sync signal, the fifo-passed subcode sync and relates the position of the subcode sync to the audio data (dac output). this flag may also be used in a super fifo or in the synchronization of different players. the output flags can be made available at bit 4 of the ebu data format (lsb of the 24-bit data word), if selected by register a. fig.9 flag output timing diagram. handbook, full pagewidth f1 f2 f3 f4 f5 f6 f7 f8 f1 f8 11.3/n m s 33.9/n m s 33.9/n m s mbg425 1998 feb 26 14 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 table 2 output ?ags f1 f2 f3 f4 f5 f6 f7 f8 description 0xxxxxxxno absolute time sync 1xxxxxxx absolute time sync x00xxxxxc1 frame contained no errors x01xxxxxc1 frame contained 1 error x10xxxxxc1 frame contained 2 errors x11xxxxxc1 frame uncorrectable x x x 0 0 x x 0 c2 frame contained no errors x x x 0 0 x x 1 c2 frame contained 1 error x x x 0 1 x x 0 c2 frame contained 2 errors x x x 0 1 x x 1 c2 frame contained 3 errors x x x 1 0 x x 0 c2 frame contained 4 errors x x x 1 1 x x 1 c2 frame uncorrectable xxxxx00xno interpolations xxxxx01xat least one 1-sample interpolation xxxxx10xat least one hold and no interpolations xxxxx11xat least one hold and one 1-sample interpolation 7.6.2 c2fail the c2fail pin indicates that invalid data has occurred on the i 2 s-bus interface. however, due to the structure of the corrector it is impossible to determine which byte has failed. c2fail will go low for (140/n) m s when invalid data is detected, this data may then occur (15/n) m s before or after the pin is activated. 7.7 audio functions 7.7.1 d e - emphasis and phase linearity when pre-emphasis is detected in the q-channel subcode, the digital filter automatically includes a de-emphasis filter section. when de-emphasis is not required, a phase compensation filter section controls the phase of the digital oversampling filter to 1 within the band 0 to 16 khz. with de-emphasis the filter is not phase linear. if the de-emphasis signal is set to be available at v5, selected via register d, then the de-emphasis filter is bypassed. 7.7.2 d igital oversampling filter the SAA7374 contains a 2 to 4 times oversampling iir filter. the filter specification of the 4 times oversampling filter is given in table 3. these attenuations do not include the sample-and-hold at the external dac output or the dac post filter. when using the oversampling filter, the output level is scaled down by - 0.5 db, to avoid overflow on full scale sine wave inputs (0 to 20 khz). table 3 filter speci?cation pass band stop band attenuation 0 to 19 khz - 0.001 db 19 to 20 khz - 0.03 db - 24 khz 3 25 db - 24 to 27 khz 3 38 db - 27 to 35 khz 3 40 db - 35 to 64 khz 3 50 db - 64 to 68 khz 3 31 db - 68 khz 3 35 db - 69 to 88 khz 3 40 db 1998 feb 26 15 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 7.7.3 c oncealment a 1-sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected. the erroneous sample is replaced by a level midway between the preceding and following samples. left and right channels have independent interpolators. if more than one consecutive non-correctable sample is found, the last good sample is held. a 1-sample linear interpolation is then performed before the next good sample (see fig.10). in cd-rom modes (i.e. the dac interface is selected to be in a cd-rom format) concealment is not executed. 7.7.4 m ute , full - speed , attenuation and fade a digital level controller is present on the SAA7374 which performs the functions of soft mute, full scale, attenuation and fade; these are selected via register 0. mute: signal reduced to 0 in a maximum of 128 steps; (3/n) m s. attenuate: signal scaled by - 12 db. full scale: ramp signal back to 0 db level. from mute takes (3/n) m s. fade: activates a 128 stage counter which allows the signal to be scaled up/down by 0.07 db steps 128 = full scale. 120 = - 0.5 db (i.e. full scale if oversampling filter used). 32 = - 12 db. 0 = mute. 7.7.5 p eak detector the peak detector measures the highest audio level (absolute value) on positive peaks for left and right channels. the 8 most significant bits are output in the q-channel data in place of the crc bits. bits 81 to 88 contain the left peak value (bit 88 = msb) and bits 89 to 96 contain the right peak value (bit 96 = msb). the values are reset after reading q-channel data via sda. fig.10 concealment mechanism. interpolation hold interpolation mga372 ok error ok error error error ok ok 1998 feb 26 16 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 7.8 dac interface the SAA7374 is compatible with a wide range of digital-to-analog converters (dacs). eleven formats are supported and are given in table 4. figures 11 and 12 show the philips i 2 s-bus and the eiaj data formats respectively. when the decoder is operated in the lock-to-disc mode, the sclk frequency is dependent on the disc speed factor d. all formats are msb first and f s is (44.1 n) khz. the polarity of the wclk and the data can be inverted; selectable by register 7. it should be noted that ef is only a defined output in cd-rom modes and 1f s modes. table 4 dac interface formats note 1. in this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated then the first 18 bits contain data. register 3 sample frequency number of bits sclk (mhz) format interpolation 1010 f s 16 2.1168 n cd-rom (i 2 s-bus) no 1011 f s 16 2.1168 n cd-rom (eiaj) no 1110 f s 16/18 (1) 2.1168 n philips i 2 s-bus 16/18 bits (1) yes 0010 f s 16 2.1168 n eiaj 16 bits yes 0110 f s 18 2.1168 n eiaj 18 bits yes 0000 4f s 16 8.4672 n eiaj 16 bits yes 0100 4f s 18 8.4672 n eiaj 18 bits yes 1100 4f s 18 8.4672 n philips i 2 s-bus 18 bits yes 0011 2f s 16 4.2336 n eiaj 16 bits yes 0111 2f s 18 4.2336 n eiaj 18 bits yes 1111 2f s 18 4.2336 n philips i 2 s-bus 18 bits yes 1998 feb 26 17 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... left channel data (wclk normal polarity) sclk 15 14 15 14 10 data wclk lsb error flag msb error flag lsb error flag msb error flag 0 1 mgd022 ef (cd-rom and 1f s modes only) fig.11 philips i 2 s-bus data format (16-bit word length shown). sclk 17 17 0 data wclk ef (cd-rom and 1f s modes only) 0 left channel data msb error flag lsb error flag msb error flag mgd021 fig.12 eiaj data format (18-bit word length shown). 1998 feb 26 18 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 7.9 ebu interface the bi-phase mark digital output signal at pin dobm is in accordance with the format defined by the iec958 specification. three different modes can be selected via register a; dobm pin held low. data taken before concealment, mute and fade (must always be used for cd-rom modes). data taken after concealment, mute and fade. 7.9.1 f ormat the digital audio output consists of 32-bit words (subframes) transmitted in bi-phase mark code (two transitions for a logic 1 and one transition for a logic 0). words are transmitted in blocks of 384.table 5 gives the formats. table 5 format table 6 description of table 5 function bits description sync 0 to 3 - auxiliary 4 to 7 not used; normally zero error ?ags 4 cflg error and interpolation ?ags when selected by register a audio sample 8 to 27 ?rst 4 bits not used (always zero). 2s compliment. lsb = bit 12, msb = bit 27 validity ?ag 28 valid = logic 0 user data 29 used for subcode data (q-to-w) channel status 30 control bits and category code parity bit 31 even parity for bits 4 to 30 function description sync the sync word is formed by violation of the bi-phase rule and therefore does not contain any data. its length is equivalent to 4 data bits. the 3 different sync patterns indicate the following situations: sync b: start of a block (384 words), word contains left sample; sync m: word contains left sample (no block start) and sync w: word contains right sample. audio sample left and right samples are transmitted alternately. validity ?ag audio samples are ?agged (bit 28 = 1) if an error has been detected but was uncorrectable. this ?ag remains the same even if data is taken after concealment. user data subcode bits q-to-w from the subcode section are transmitted via the user data bit. this data is asynchronous with the block rate. channel status the channel status bit is the same for left and right words. therefore a block of 384 words contains 192 channel status bits. the category code is always cd. the bit assignment is given in table 7. 1998 feb 26 19 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 table 7 bit assignment function bits description control 0 to 3 copy of crc checked q-channel control bits 0 to 3; bit 2 is logic 1 when copy permitted; bit 3 is logic 1 when recording has pre-emphasis reserved mode 4 to 7 always zero category code 8 to 15 cd: bit 8 = logic 1, all other bits = logic 0 clock accuracy 28 to 29 set by register a; 10 = level i; 00 = level ii; 01 = level iii remaining 16 to 27 and 30 to 191 always zero 7.10 kill circuit the kill circuit detects digital silence by testing for an all-zero or all-ones data word in the left or right channel before the digital filter. the output is switched active low when silence has been detected for at least 250 ms, or if mute is active, or in cd-rom modes. two modes are available which can be selected by register c 1 pin kill: kill active low indicates silence detected on both left and right channels. 2 pin kill: kill active low indicates silence detected on left channel. v3 active low indicates silence detected on right channel. it should be noted that when mute is active or in cd-rom modes the output(s) are switched low. 7.11 audio features off the audio features can be turned off (selected by register e) which affects the following functions; digital filter, fade, peak detector, kill circuit (but outputs kill, v3 still active) are disabled. v5 (if selected to be the de-emphasis flag output) and the ebu outputs become undefined. it should be noted that the ebu output should be set low prior to switching the audio features off and after switching audio features back on a full-scale command should be given. 1998 feb 26 20 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 7.12 the via interface the SAA7374 has five pins that can be reconfigured for different applications (see table 8). table 8 pin applications pin name pin number type control register address control register data function v1 62 input 1100 xxx1 external off-track signal input - xxx0 internal off-track signal used, input may be read via decoder status bit; selected via register 2 v2 63 input -- input may be read via decoder status bit; selected via register 2 v3 42 output 1100 xx0x kill output for right channel - x01x output = 0 - x11x output = 1 v4 41 output 1101 0000 4-line motor drive (using v4 and v5) - xx01 q-to-w subcode output - xx10 output = 0 - xx11 output = 1 v5 40 output 1101 01xx de-emphasis output (active high) - 10xx output = 0 - 11xx output = 1 7.13 spindle motor control 7.13.1 m otor output modes the spindle motor speed is controlled by a fully integrated digital servo. address information from the internal 8 frame fifo and disc speed information are used to calculate the motor control output signals. several output modes, selected by register 6, are supported: pulse density, 2-line (true complement output), (1 n) mhz sample frequency pwm output, 2-line, (22.05 n) khz modulation frequency pwm output, 4-line, (22.05 n) khz modulation frequency cdv motor mode. 7.13.1.1 pulse density output mode in the pulse density mode the motor output pin (moto1) is the pulse density modulated motor output signal. a 50% duty factor corresponds with the motor not actuated, higher duty factors mean acceleration, lower mean braking. in this mode, the moto2 signal is the inverse of the moto1 signal. both signals change state only on the edges of a (1 n) mhz internal clock signal. possible application diagrams are illustrated in fig.13. 7.13.1.2 pwm output mode (2-line) in the pwm mode the motor acceleration signal is put in pulse-width modulation form on the moto1 output. the motor braking signal is pulse-width modulated on the moto2 output. the timing is illustrated in fig.14. a typical application diagram is illustrated in fig.15. 1998 feb 26 21 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 fig.13 motor pulse density application diagrams. mga363 - 1 moto2 v dd v ss moto1 m 22 k w 10 nf + 22 k w 10 nf + v ss v ss moto1 m 22 k w 10 nf + 22 k w 22 k w v ss v dd v ss 22 k w 22 k w fig.14 2-line pwm mode timing. rep t = 45 m s t 240 ns dead accelerate brake moto1 moto2 mga366 fig.15 motor 2-line pwm mode application diagram. mga365 - 2 v ss + m moto1 moto2 10 w 100 nf 1998 feb 26 22 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 7.13.1.3 pwm output mode (4-line) using two extra outputs from the versatile pins interface, it is possible to use the SAA7374 with a 4-input motor bridge. the timing is illustrated in fig.16. a typical application diagram is illustrated in fig.17. fig.16 4-line pwm mode timing. moto1 moto2 v4 v5 rep t = 45 m s t 240 ns dead ovl t = 240 ns accelerate brake mga367 - 1 fig.17 motor 4-line pwm mode application diagram. mga364 - 2 v ss + m moto1 v4 moto2 v5 100 nf 10 w 1998 feb 26 23 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 7.13.1.4 cdv/cav output mode in the cdv motor mode, the fifo position will be put in pulse-width modulated form on the moto1 pin [carrier frequency (300 d) hz], where d is the disc speed factor. the pll frequency signal will be put in pulse-density modulated form (carrier frequency 4.23 n mhz) on the moto2 pin. the integrated motor servo is disabled in this mode. the pwm signal on moto1 corresponds to a total memory space of 20 frames, therefore the nominal fifo position (half full) will result in a pwm output of 60%. in the lock to-disc (cav) mode the cdv motor mode is the only mode that can be used to control the motor. 7.13.2 s pindle motor operating modes the motor servo has the following operation modes controlled by register 1 (see table 9). in the SAA7374 decoder there is an anti-wind-up mode for the motor servo, selected via register 1. when the anti-wind-up mode is activated the motor servo integrator will hold if the motor output saturates. 7.13.2.1 power limit in start mode 1, start mode 2, stop mode 1 and stop mode 2, a fixed positive or negative voltage is applied to the motor. this voltage can be programmed as a percentage of the maximum possible voltage, via register 6, to limit current drain during start and stop. the following power limits are possible; 100% (no power limit), 75%, 50%, or 37% of maximum. 7.13.3 l oop characteristics the gain and crossover frequencies of the motor control loop can be programmed via registers 4 and 5. the following parameter values are possible; gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6 and 32 crossover frequency f 4 : 0.5 n hz, 0.7 n hz, 1.4 n hz, 2.8 nhz crossover frequency f 3 : 0.85 n hz, 1.71 n hz, 3.42 nhz it should be noted that the crossover frequencies f 3 and f 4 are scaled with the overspeed factor n whereas the gains are not. 7.13.4 fifo overflow if fifo overflow occurs during play mode (e.g. as a result of motor rotational shock), the fifo will be automatically reset to 50% and the audio interpolator tries to conceal as much as possible to minimise the effect of data loss. table 9 operating modes mode description start mode 1 the disc is accelerated by applying a positive voltage to the spindle motor. no decisions are involved and the pll is reset. no disc speed information is available for the microcontroller. start mode 2 the disc is accelerated as in start mode 1, however the pll will monitor the disc speed. when the disc reaches 75% of its nominal speed, the controller will switch to jump mode. the motor status signals selectable via register 2 are valid. jump mode motor servo enabled but fifo kept reset at 50%, integrator is held. the audio is muted but it is possible to read the subcode. it should be noted that in the cd-rom modes the data, on ebu and the i 2 s-bus is not muted. jump mode 1 similar to jump mode but motor integrator is kept at zero. used for long jumps where there is a large change in disc speed. play mode fifo released after resetting to 50%. audio mute released. stop mode 1 disc is braked by applying a negative voltage to the motor. no decisions are involved. stop mode 2 the disc is braked as in stop mode 1 but the pll will monitor the disc speed. as soon as the disc reaches 12% (or 6%, depending on the programmed brake percentage, via register e) of its nominal speed, the motstop status signal will go high and switch the motor servo to off mode. off mode motor not steered. 1998 feb 26 24 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 fig.18 motor servo mode diagram. mga362 - 2 g f 4 fbw 3 f 7.14 servo part 7.14.1 d iode signal processing the photo detector in conventional two-stage three-beam compact disc systems normally contains six discrete diodes. four of these diodes (three for single foucault systems) carry the central aperture signal (ca) while the other two diodes (satellite diodes) carry the radial tracking information. the ca signal is processed into an hf signal (for the decoder function) and lf signal (information for the focus servo loop) before it is supplied to the SAA7374. the analog signals from the central and satellite diodes are converted into a digital representation using analog-to-digital converters (adcs). the adcs are designed to convert unipolar currents into a digital code. the dynamic range of the input currents is adjustable within a given range, which is dependent on the value of external resistor connected to pin i reft . the maximum current for the central diodes and satellite diodes is given in the following formulae; m a m a the v rh voltage is internally generated by control circuitry which ensures that the v rh voltage is adjusted depending on the spread of internal capacitors, using the reference i in max central , () 2.4 10 6 C r ireft ------------------------- - ? ? ?? = i in max satellite , () 1.2 10 6 C r ireft ------------------------- - ? ? ?? = current generated by the external resistor on i reft . in the application v rl is connected to v ssa1 . the maximum input currents for a range of resistors is given table 10. table 10 maximum current input this mode of v rh automatic adjustment can be selected by the preset latch command. alternatively, the dynamic range of the input currents can be made dependent on the adc reference voltages v rl and v rh . the maximum current for the central diodes and satellite diodes is given in the following formulae; r ireft (k w ) diode input current range d1 to d4 ( m a) r1 and r2 ( m a) 220 10.909 5.455 240 10.000 5.000 270 8.889 4.444 300 8.000 4.000 330 7.273 3.636 360 6.667 3.333 390 6.154 3.077 430 5.581 2.791 470 5.106 2.553 510 4.706 2.353 560 4.286 2.143 620 3.871 1.935 1998 feb 26 25 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 m a m a where f sys = 4.2336 mhz. v rh is generated internally, and there are 32 levels which can be selected under software control via the preset latch command. with this command the v rh voltage can be set to 2.5 v then modified, decremented one level or incremented, by resenting the command the required number of times. in the application v rl is connected to v ssa1 . 7.14.2 s ignal conditioning the digital codes retrieved from the adcs are applied to logic circuitry to obtain the various control signals. the signals from the central aperture diodes are processed to obtain a normalised focus error signal. where the detector set-up is assumed as shown in fig.19. in the event of single foucault focusing method, the signal conditioning can be switched under software control such that the signal processing is as follows; i in max central , () f sys v rh v rl C () 1.0 10 6 C = i in max satellite , () f sys v rh v rl C () 0.5 10 6 C = fe n d1 d2 C d1 d2 + ---------------------- d3 d4 C d3 d4 + ---------------------- C = fe n 2 d1 d2 C d1 d2 + ---------------------- = the error signal, fe n , is further processed by a proportional integral and differential (pid) filter section. a focus ok (fok) flag is generated by means of the central aperture signal and an adjustable reference level. this signal is used to provide extra protection for the track-loss (tl) generation, the focus start-up procedure and the drop out detection. the radial or tracking error signal is generated by the satellite detector signals r1 and r2. the radial error signal can be formulated as follows; where the index s indicates the automatic scaling operation which is performed on the radial error signal. this scaling is necessary to avoid non-optimum dynamic range usage in the digital representation and reduces the radial bandwidth spread. furthermore, the radial error signal will be made free from offset during start up of the disc. the four signals from the central aperture detectors, together with the satellite detector signals generate a track position signal (tpi) which can be formulated as follows; tpi = sign [(d1 + d2 + d3 + d4) - (r1 + r2) sum_gain] where the weighting factor sum_gain is generated internally by the SAA7374 during initialization. r e s r1 r2 C () re_gain r1 r2 C () re_offse t + = fig.19 detector arrangement. handbook, full pagewidth d3 d1 d2 satellite diode r1 satellite diode r2 d1 d3 d2 d4 satellite diode r1 satellite diode r2 d1 d2 d3 d4 satellite diode r1 satellite diode r2 single foucault astigmatic focus double foucault mbg422 1998 feb 26 26 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 7.14.3 f ocus servo system 7.14.3.1 focus start-up five initially loaded coefficients influence the start-up behaviour of the focus controller. the automatically generated triangle voltage can be influenced by 3 parameters; for height (ramp_height) and dc offset (ramp_offset) of the triangle and its steepness (ramp_incr). for protection against false focus point detections two parameters are available which are an absolute level on the ca-signal (ca_start) and a level on the fe n signal (fe_start). when this ca level is reached the fok signal becomes true. if the fok signal is true and the level on the fe n signal is reached, the focus pid is enabled to switch on when the next zero crossing is detected in the fe n signal. 7.14.3.2 focus position control loop the focus control loop contains a digital pid controller which has 5 parameters which are available to the user. these coefficients influence the integrating (foc_int), proportional (foc_lead_length, part of foc_parm3) and differentiating (foc_pole_lead, part of foc_parm1) action of the pid and a digital low-pass filter (foc_pole_noise, part of foc_parm2) following the pid. the fifth coefficient foc_gain influences the loop gain. 7.14.3.3 drop-out detection this detector can be influenced by one parameter (ca_drop). the fok signal will become false and the integrator of the pid will hold if the ca signal drops below this programmable absolute ca level. when the fok signal becomes false it is assumed, initially, to be caused by a black dot. 7.14.3.4 focus loss detection and fast restart whenever fok is false for longer than approximately 3 ms, it is assumed that the focus point is lost. a fast restart procedure is initiated which is capable of restarting the focus loop within 200 to 300 ms depending on the programmed coefficients of the microcontroller. 7.14.3.5 focus loop gain switching the gain of the focus control loop (foc_gain) can be multiplied by a factor of 2 or divided by a factor of 2 during normal operation. the integrator value of the pid is corrected accordingly. the differentiating (foc_pole_lead) action of the pid can be switched at the same time as the gain switching is performed. 7.14.3.6 focus automatic gain control loop the loop gain of the focus control loop can be corrected automatically to eliminate tolerances in the focus loop. this gain control injects a signal into the loop which is used to correct the loop gain. since this decreases the optimum performance, the gain control should only be activated for a short time (for example, when starting a new disc). 7.14.4 r adial servo system 7.14.4.1 level initialization during start-up an automatic adjustment procedure is activated to set the values of the radial error gain (re_gain), offset (re_offset) and satellite sum gain (sum_gain) for tpi level generation. the initialization procedure runs in a radial open loop situation and is 300 ms. this start-up time period may coincide with the last part of the motor start-up time period. automatic gain adjustment: as a result of this initialization the amplitude of the re signal is adjusted within 10% around the nominal re amplitude. offset adjustment: the additional offset in re due to the limited accuracy of the start-up procedure is less than 50 nm. tpi level generation: the accuracy of the initialization procedure is such that the duty factor range of tpi becomes 0.4 < duty factor < 0.6 (definition of duty factor = tpi high/tpi period). 7.14.4.2 sledge control the microcontroller can move the sledge in both directions via the steer sledge command. 7.14.4.3 tracking control the actuator is controlled using a pid loop filter with user defined coefficients and gain. for stable operation between the tracks, the s-curve is extended over 0.75 track. on request from the microcontroller, s-curve extension over 2.25 tracks is used, automatically changing to access control when exceeding those 2.25 tracks. both modes of s-curve extension make use of a track-count mechanism. in this mode, track counting results in an automatic return-to-zero track, to avoid major music rhythm disturbances in the audio output for improved shock resistance. 1998 feb 26 27 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 the sledge is continuously controlled, or provided with step pulses to reduce power consumption using the filtered value of the radial pid output. alternatively, the microcontroller can read the average voltage on the radial actuator and provide the sledge with step pulses to reduce power consumption. filter coefficients of the continuous sledge control can be preset by the user. 7.14.4.4 access the access procedure is divided into two different modes (see table 11), depending on the requested jump size. table 11 access modes note 1. microcontroller presettable. the access procedure makes use of a track counting mechanism, a velocity signal based on a fixed number of tracks passed within a fixed time interval, a velocity set point calculated from the number of tracks to go and a user programmable parameter indicating the maximum sledge performance. if the number of tracks to go is greater than the brake_distance then the sledge jump mode should be activated or, the actuator jump should be performed. the requested jump size together with the required sledge breaking distance at maximum access speed defines the brake_distance value. during the actuator jump mode, velocity control with a pi controller is used for the actuator. the sledge is then continuously controlled using the filtered value of the radial pid output. all filter parameters (for actuator and sledge) are user programmable. in the sledge jump mode maximum power (user programmable) is applied to the sledge in the correct direction while the actuator becomes idle (the contents of the actuator integrator leaks to zero just after the sledge jump mode is initiated). access type jump size (1) access speed actuator jump 1 - brake_distance decreasing velocity sledge jump brake_distance - 32768 maximum power to sledge (1) 7.14.4.5 radial automatic gain control loop the loop gain of the radial control loop can be corrected automatically to eliminate tolerances in the radial loop. this gain control injects a signal into the loop which is used to correct the loop gain. since this decreases the optimum performance, the gain control should only be activated for a short time (for example, when starting a new disc). this gain control differs from the level initialization. the level initialization should be performed first. the disadvantage of using the level initialization without the gain control is that only tolerances from the front-end are reduced. 7.14.5 o ff - track counting the track position signal (tpi) is a flag which is used to indicate whether the radial spot is positioned on the track, with a margin of 1 4 of the track-pitch. in combination with the radial polarity flag (rp) the relative spot position over the tracks can be determined. these signals are, however, afflicted with some uncertainties caused by; disc defects such as scratches and fingerprints the hf information on the disc, which is considered as noise by the detector signals. in order to determine the spot position with sufficient accuracy, extra conditions are necessary to generate a track loss signal (tl) and an off-track counter value. these extra conditions influence the maximum speed and this implies that, internally, one of the following three counting states is selected: 1. protected state: used in normal play situations. a good protection against false detection caused by disc defects is important in this state. 2. slow counting state: used in low velocity track jump situations. in this state a fast response is important rather than the protection against disc defects (if the phase relationship between tl and rp of 1 2 p radians is affected too much, the direction cannot then be determined accurately). 3. fast counting state: used in high velocity track jump situations. highest obtainable velocity is the most important feature in this state. 1998 feb 26 28 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 7.14.6 d efect detection fig.20 block diagram of defect detector. handbook, full pagewidth decimation filter fast filter defect generation programmable hold-off slow filter defect output sat1 sat2 + - mbg421 a defect detection circuit is incorporated into the SAA7374. if a defect is detected, the radial and focus error signals may be zeroed, resulting in better playability. the defect detector can be switched off, applied only to focus control or applied to both focus and radial controls under software control (part of foc_parm1). the defect detector (see fig.20) has programmable set points selectable by the parameter defect_parm. 7.14.7 o ff - track detection during active radial tracking, off-track detection has been realised by continuously monitoring the off-track counter value. the off-track flag becomes valid whenever the off-track counter value is not equal to zero. depending on the type of extended s-curve, the off-track counter is reset after 0.75 extend or at the original track in the 2.25 track extend mode. 7.14.8 high level features 7.14.8.1 interrupt mechanism and status pin the status pin is an output which is active low, its output is selected by register 7 to be either the status bit (active low) selected by register 2 (only available in 4-wire bus mode) or the interrupt signal generated by the servo part. 8 signals from the interrupt status register are selectable from the servo part via the interrupt_mask parameter. the interrupt is reset by sending the read high-level status command. the 8 signals are listed below. 1. focus lost: drop out of longer than 3 ms. 2. subcode ready. 3. subcode absolute seconds changed. 4. subcode discontinuity detected: new subcode time before previous subcode time, or more than 10 frames later than previous subcode time. 5. radial error: during radial on-track, no new subcode frame occurs within time defined by playwatchtime parameter. during radial jump, less than 4 tracks have been crossed during time defined by jumpwatchtime parameter. 6. autosequencer state change. 7. autosequencer error. 8. subcode interface blocked: the internal decoder interface is being used. it should be noted that if the status pin output is selected via register 2 and either the microcontroller writes a different value to register 2 or the decoder interface is enabled then the status output will change. 7.14.8.2 decoder interface the decoder interface allows registers 0 to f to be programmed and subcode q-channel data to be read via servo commands. the interface is enabled/disabled by the preset latch command (and the xtra_preset parameter) 7.14.8.3 automatic error handling three watchdogs are present; 1. focus: detects focus drop out of longer than 3 ms, sets focus lost interrupt, switches off radial and sledge servos, disables drive to disc motor. 2. radial play: started when radial servo is on-track mode and a first subcode frame is found. detects when maximum time between two subcode frames exceeds time set by playwatchtime parameter; then sets radial error interrupt, switches radial and sledge servos off, puts disc motor in jump mode. 3. radial jump: active when radial servo in long jump or short jump modes. detects when the off-track counter value decreases by less than 4 tracks between two readings (time interval set by jumpwatchtime parameter); then sets radial jump error, switches radial and sledge servos off to cancel jump. the focus watchdog is always active, the radial watchdogs are selectable via the r adcontrol parameter. 1998 feb 26 29 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 7.14.8.4 automatic sequencers and timer interrupts two automatic sequencers are implemented (and must be initialized after power on); 1. autostart sequencer: controls the start-up of focus, radial and motor. 2. autostop sequencer: brakes the disc and shuts down servos. when the automatic sequencers are not used it is possible to generate timer interrupts, defined by the time_parameter coefficient. 7.14.8.5 high-level status the read high-level status command can be used to obtain the interrupt, decoder, autosequencer status registers and the motor start time. use of the read high-level status command clears the interrupt status register, and re-enables the subcode read via a servo command. 7.14.9 d river interface the control signals (pins ra, fo and sl) for the mechanism actuators are pulse density modulated. the modulating frequency can be set to either 1.0584 mhz (dsd mode) or 2.1168 mhz; controlled via the xtra_preset parameter. an analog representation of the output signals can be achieved by connecting a first-order low-pass filter to the outputs. during reset (i.e. reset pin is held low) the ra, fo and sl pins are high-impedance. 7.14.10 l aser interface the ldon pin (open-drain output) is used to switch the laser off and on. when the laser is on the output is high-impedance. the action of the ldon pin is controlled by the xtra_preset parameter; the pin is automatically driven if the focus control loop is active. 7.14.11 r adial shock detector the shock detector (see fig.21) can be switched on during normal track following, and detects within an adjustable frequency whether disturbances in the radial spot position relative to the track exceed an adjustable level (controlled by shock_level ). every time the radial tracking error (re) exceeds this level the radial control bandwidth is switched to twice its original bandwidth and the loop gain is increased by a factor of 4. the shock detection level is adjustable in 16 steps from 0 to 100% of the traverse radial amplitude which is sent to an amplitude detection unit via an adjustable band-pass filter (controlled by sledge_parm1 ); lower corner frequency can be set at either 0 or 20 hz, and upper corner frequency at 750 or 1850 hz. the shock detector is switched off automatically during jump mode. fig.21 block diagram of radial shock detector. handbook, full pagewidth re mgc914 shock output high-pass filter (0 or 20 hz) low-pass filter (750 or 1850 hz) amplitude detection 1998 feb 26 30 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 7.15 microcontroller interface communication on the microcontroller interface can be set-up in two different modes; 1. 4-wire bus mode: protocol compatible with saa7345 (cd6) and tda1301 (dsic2) where; a) scl = serial bit clock. b) sda = serial data. c) rab = r/ w control and data strobe (active high) for writing to registers 0 to f, reading status bit selected via register 2 and reading q-channel subcode. d) sild = r/w control and data strobe (active low) for servo commands. 2. i 2 c-bus mode: i 2 c-bus protocol where SAA7374 behaves as slave device. activated by setting rab = high and sild = low where; a) i 2 c-bus slave address (write mode) = 30h. b) i 2 c-bus slave address (read mode) = 31h. c) maximum data transfer rate = 400 kbits/s. it should be noted that only servo commands can be used therefore, writing to registers 0 to f, reading decoder status and reading q-channel subcode data must be performed by servo commands. 7.15.1 microcontroller interface (4- wire bus mode ) 7.15.1.1 writing data to registers 0 to f the sixteen 4-bit programmable configuration registers, 0 to f (see table 12), can be written to via the microcontroller interface using the protocol shown in fig.22. it should be noted that sild must be held high; a3 to a0 identifies the register number and d3 to d0 is the data; the data is latched into the register on the low-to-high transition of rab. 7.15.1.2 writing repeated data to registers 0 to f the same data can be repeated several times (e.g. for a fade function) by applying extra rab pulses as shown in fig.23. it should be noted that scl must stay high between rab pulses. 7.15.1.3 reading decoder status information on sda there are several internal status signals, selected via register 2, which can be made available on the sda line; subqready-i: low if new subcode word is ready in q-channel register. motstart1: high if motor is turning at 75% or more of nominal speed. motstart2: high if motor is turning at 50% or more of nominal speed. motstop: high if motor is turning at 12% or less of nominal speed. can be set to indicate 6% or less (instead of 12% or less) via register e. pll lock: high if sync coincidence signals are found. v1: follows input on v1 pin. v2: follows input on v2 pin. motor-ov: high if the motor servo output stage saturates. fifo-ov: high if fifo overflows. shock: motstart2 + pll lock + motor-ov + fifo-ov + servo interrupt signal + otd (high if shock detected) la-shock: latched shock signal the status read protocol is shown in fig.24. it should be noted that sild must be held high. 7.15.1.4 reading q-channel subcode to read the q-channel subcode direct in the 4-wire bus mode, the subqready-i signal should be selected as status signal. the subcode read protocol is illustrated in fig.25. it should be noted that sild must be held high; after subcode read starts, the microcontroller may take as long as it wants to terminate the read operation; when enough subcode has been read (1 to 96 bits), terminate reading by pulling rab low. alternatively, the q-channel subcode can be read using a servo command as follows; use the read high-level status command to monitor the subcode ready signal send the read subcode command, and read the required number of bytes (up to 12) send the read high-level status command; to re-enable the decoder interface. 7.15.1.5 behaviour of the subqready-i signal when the crc of the q-channel word is good, and no subcode is being read, the subqready-i status signal will react as shown in fig.26. when the crc is good and subcode is being read, the timing in fig.27 applies. 1998 feb 26 31 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 if t 1 (subqready-i status low to end of subcode read) is below (2.6/n) ms, then t 2 = (13.1/n) ms [i.e. the microcontroller can read all subcode frames if it completes the read operation within (2.6/n) ms after the subcode is ready]. if this criterion is not met, it is only possible to guarantee that t 3 will be below (26.2/n) ms (approximately). if subcode frames with failed crcs are present, the t 2 and t 3 times will be increased by (13.1/n) ms for each defective subcode frame. it should be noted that in the lock-to-disc mode n is replaced by d, which is the disc speed factor. 7.15.1.6 write servo commands a write data command is used to transfer data (a number of bytes) from the microcontroller, using the protocol shown in fig.28. the first of these bytes is the command byte and the following are data bytes; the number (between 1 and 7) depends on the command byte. it should be noted that rab must be held low; the command or data is interpreted by the SAA7374 after the high-to-low transition of sild; there must be a minimum time of 70 m s between sild pulses. 7.15.1.7 writing repeated data in servo commands the same data byte can be repeated by applying extra sild pulses as shown in fig.29. scl must stay high between the sild pulses 7.15.1.8 read servo commands a read data command is used to transfer data (status information) to the microcontroller, using the protocol shown in fig.30. the first byte written determines the type of command. after this byte a variable number of bytes can be read. it should be noted that rab must be held low; after the end of command byte (low-to-high transition on sild) there must be a delay of 70 m s before reading data is started (i.e. on the next high-to-low transition of sild); there must be a minimum time of 70 m s between sild pulses. 7.15.2 m icrocontroller interface (i 2 c- bus mode ) bytes are transferred over the interface in groups (i.e. servo commands) of which there are two types: write data commands and read data commands. the sequence for a write data command (that requires 3 data bytes) is as follows; send start condition send address 30h (write) write command byte write data byte 1 write data byte 2. write data byte 3 send stop condition. it should be noted that more than one command can be sent in one write sequence. the sequence for a read data command (that reads 2 data bytes) is as follows: send start condition send address 30h (write) write command byte send stop condition. send start condition send address 31h (read) read data byte 1 read data byte 2 send stop condition. it should be noted that the timing constraints specified for the read and write servo commands must still be adhered to. 1998 feb 26 32 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 fig.22 microcontroller write protocol for registers 0 to f. a3 a2 a1 a0 d3 d2 d1 d0 sda (SAA7374) scl (microcontroller) rab (microcontroller) sda (microcontroller) mbg657 high-impedance fig.23 microcontroller write protocol for registers 0 to f (repeat mode). a3 a2 a1 a0 d3 d2 d1 d0 sda (SAA7374) mbg656 scl (microcontroller) rab (microcontroller) sda (microcontroller) high-impedance fig.24 microcontroller read protocol for decoder status on sda. sda (SAA7374) mbg651 status scl (microcontroller) rab (microcontroller) sda (microcontroller) high-impedance 1998 feb 26 33 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 fig.25 microcontroller protocol for reading q-channel subcode. q1 q2 q3 qn? sda (SAA7374) mbg652 qn? qn status crc ok scl (microcontroller) rab (microcontroller) fig.26 subqready-i status timing when no subcode is read. sda (SAA7374) 10.8/n ms 15.4/n ms 2.3/n ms read start allowed high impedance crc ok crc ok mbg653 scl (microcontroller) rab (microcontroller) 1998 feb 26 34 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 fig.27 subqready-i status timing when subcode is read. q1 q2 q3 qn sda (SAA7374 ) t 1 t 2 t 3 mbg654 scl (microcontroller) rab (microcontroller) fig.28 microcontroller protocol for write servo commands. handbook, full pagewidth d7 d6 d5 d4 d3 d2 d1 d0 sda (SAA7374) sild (microcontroller) scl (microcontroller) sda (microcontroller) sild (microcontroller) sda (microcontroller) command data1 data2 data3 command or data byte high-impedance microcontroller write (one byte: command or data) microcontroller write (full command) mbg655 1998 feb 26 35 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 fig.29 microcontroller protocol for repeated data in write servo commands. handbook, full pagewidth sild (microcontroller) sda (microcontroller) microcontroller write (full command) command data1 mbg413 fig.30 microcontroller protocol for read servo commands. handbook, full pagewidth data1 data2 data3 command sild (microcontroller) sild (microcontroller) scl (microcontroller) sda (microcontroller) sda (SAA7374) sda (SAA7374) d7 d6 d5 d4 d3 d2 d1 d0 data byte microcontroller read (one data byte) microcontroller read (full command) mbg659 1998 feb 26 36 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 7.15.3 s ummary of functions controlled by registers 0 to f table 12 registers 0 to f register address data function initial (1) 0 (fade and attenuation) 0000 0000 mute reset 0010 attenuate - 0001 full scale - 0100 step down - 0101 step up - 1 (motor mode) 0001 x000 motor off mode reset x 001 motor stop mode 1 - x010 motor stop mode 2 - x011 motor start mode 1 - x100 motor start mode 2 - x101 motor jump mode - x111 motor play mode - x110 motor jump mode 1 - 1xxx anti-windup active - 0xxx anti-windup off reset 2 (status control) 0010 0000 status = subqready-i reset 0001 status = motstart1 - 0010 status = motstart2 - 0011 status = motstop - 0100 status = pll lock - 0101 status = v1 - 0110 status = v2 - 0111 status = motor-ov - 1000 status = fifo over?ow - 1001 status = shock detect - 1010 status = latched shock detect - 1011 status = latched shock detect reset - 3 (dac output) 0011 1010 i 2 s-bus; cd-rom mode - 1011 eiaj; cd-rom mode - 1100 i 2 s-bus; 18-bit; 4f s mode reset 1111 i 2 s-bus; 18-bit; 2f s mode - 1110 i 2 s-bus; 16-bit; f s mode - 0000 eiaj; 16-bit; 4f s - 0011 eaij; 16-bit; 2f s - 0010 eiaj; 16-bit; f s - 0100 eiaj; 18-bit; 4f s - 0111 eiaj; 18-bit; 2f s - 0110 eiaj; 18-bit; f s - 1998 feb 26 37 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 4 (motor gain) 0100 x000 motor gain g = 3.2 reset x001 motor gain g = 4.0 - x010 motor gain g = 6.4 - x011 motor gain g = 8.0 - x100 motor gain g = 12.8 - x101 motor gain g = 16.0 - x110 motor gain g = 25.6 - x111 motor gain g = 32.0 - 0xxx disable comparator clock divider reset 1xxx enable comparator clock divider; only if sellpll set high - 5 (motor bandwidth) 0101 xx00 motor f4 = 0.5 n hz reset xx01 motor f4 = 0.7 nhz - xx10 motor f4 = 1.4 nhz - xx11 motor f4 = 2.8 nhz - 00xx motor f3 = 0.85 n hz reset 01xx motor f3 = 1.71 nhz - 10xx motor f3 = 3.42 nhz - 6 (motor output con?guration) 0110 xx00 motor power maximum 37% reset xx01 motor power maximum 50% - xx10 motor power maximum 75% - xx11 motor power maximum 100% - 00xx moto1, moto2 pins 3-state reset 01xx motor pwm mode - 10xx motor pdm mode - 11xx motor cdv mode - 7 (dac output and status control) 0111 xx00 interrupt signal from servo at status pin reset xx10 status bit from decoder status register at status pin - x0xx dac data normal value reset x1xx dac data inverted value - 0xxx left channel ?rst at dac (wclk normal) reset 1xxx right channel ?rst at dac (wclk inverted) - 8 (pll loop ?lter bandwidth) see table 13 - 9 (pll equalization) 1001 0011 pll loop ?lter equalization reset 0001 pll 30 ns over-equalization - 0010 pll 15 ns over-equalization - 0100 pll 15 ns under-equalization - 0101 pll 30 ns under-equalization - register address data function initial (1) 1998 feb 26 38 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 a (ebu output) 1010 xx0x ebu data before concealment - xx1x ebu data after concealment and fade reset x0x0 level ii clock accuracy (<1000 ppm) reset x0x1 level i clock accuracy (<50 ppm) - x1x0 level iii clock accuracy (>1000 ppm) - x1x1 ebu off - output low - 0xxx ?ags in ebu off reset 1xxx ?ags in ebu on - b (speed control) 1011 x0xx 33.8688 mhz crystal present, or 8.4672 mhz crystal with selpll set high reset x1xx 16.9344 mhz crystal present - 0xxx single-speed mode reset 1xxx double-speed mode - xx00 standby 1: cd-stop mode reset xx10 standby 2: cd-pause mode - xx11 operating mode - c (versatile pins interface) 1100 xxx1 external off-track signal input at v1 - xxx0 internal off-track signal used (v1 may be read via status) reset xx0x kill-l at kill output, kill-r at v3 output - 001x v3 = 0; single kill output reset 011x v3 = 1; single kill output - d (versatile pins interface) 1101 0000 4-line motor (using v4 and v5) - xx01 q-to-w subcode at v4 - xx10 v4 = 0 - xx11 v4 = 1 reset 01xx de-emphasis signal at v5, no internal de-emphasis ?lter - 10xx v5 = 0 - 11xx v5 = 1 reset e 1110 00xx audio features disabled 01xx audio features enabled reset xx0x lock-to-disc mode disabled reset xx1x lock-to-disc mode enabled - xxx0 motor brakes to 12% reset xxx1 motor brakes to 6% - register address data function initial (1) 1998 feb 26 39 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 note 1. the initial column shows the power-on reset state. table 13 loop ?lter bandwidth note 1. the initial column shows the power-on reset state. f (subcode interface) 1111 x000 subcode interface off reset x100 subcode interface on - 0xxx 4-wire subcode reset 1xxx 3-wire subcode - register address data function initial (1) loop bandwidth (hz) internal bandwidth (hz) low-pass bandwidth (hz) 8 (pll loop ?lter bandwidth) 1000 0000 1640 n 525 n 8400 n - 0001 3279 n 263 n 16800 n - 0010 6560 n 131 n 33600 n - 0100 1640 n 1050 n 8400 n - 0101 3279 n 525 n 16800 n - 0110 6560 n 263 n 33600 n - 1000 1640 n 2101 n 8400 n - 1001 3279 n 1050 n 16800 n reset 1010 6560 n 525 n 33600 n - 1100 1640 n 4200 n 8400 n - 1101 3279 n 2101 n 16800 n - 1110 6560 n 1050 n 33600 n - register address data function initial (1) 1998 feb 26 40 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 7.15.4 s ummary of servo commands a list of the servo commands are given in table 14. it should be noted that these are not fully backwards compatible with dsic2. table 14 cd7 servo commands notes 1. these commands only available when internal decoder interface is enabled. 2. 1998 feb 26 41 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 7.15.5 s ummary of servo command parameters table 15 servo command parameters parameter ram address affects por value determines foc_parm_1 - focus pid - end of focus lead defect detector enabling foc_parm_2 - focus pid - focus low-pass focus error normalising foc_parm_3 - focus pid - focus lead length minimum light level foc_int 14h focus pid - focus integrator crossover frequency foc_gain 15h focus pid 70h focus pid loop gain ca_drop 12h focus pid - sensitivity of drop-out detector ramp_offset 16h focus ramp - asymmetry of focus ramp ramp_height 18h focus ramp - peak-to-peak value of ramp voltage ramp_incr - focus ramp - slope of ramp voltage fe_start 19h focus ramp - minimum value of focus error rad_parm_play 28h radial pid - end of radial lead rad_pole_noise 29h radial pid - radial low-pass rad_length_lead 1ch radial pid - length of radial lead rad_int 1eh radial pid - radial integrator crossover frequency rad_gain 2ah radial pid 70h radial loop gain rad_parm_jump 27h radial jump - ?lter during jump vel_parm1 1fh radial jump - pi controller crossover frequencies vel_parm2 32h radial jump - jump pre-de?ned pro?le speed_threshold 48h radial jump - maximum speed in fastrad mode hold_mult 49h radial jump 00h sledge bandwidth during jump brake_dist_max 21h radial jump - maximum sledge distance allowed in fast actuator steered mode sledge_long_brake 58h radial jump 7fh brake distance of sledge sledge_umax - sledge - voltage on sledge during long jump sledge_level - sledge - voltage on sledge when steered sledge_parm_1 36h sledge - sledge integrator crossover frequency sledge_parm_2 17h sledge - sledge low-pass frequencies sledge gain sledge operation mode sledge_pulse1 46h pulsed sledge - pulse width sledge_pulse2 64h pulsed sledge - pulse height defect_parm - defect detector - defect detector setting shock_level - shock detector - shock detector operation playwatchtime 54h watchdog - radial on-track watchdog time jumpwatchtime 57h watchdog - radial jump watchdog time-out 1998 feb 26 42 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 radcontrol 59h watchdog - enable/disable automatic radial off feature chip_init - set-up - v rh level setting enable/disable decoder interface xtra_preset 4ah set-up 38h laser on/off ra, fo and sl pdm modulating frequency microcontroller communication to decoder part cd6cmd 4dh decoder interface - decoder part commands interrupt_mask 53h status pin - enabled interrupts seq_control 42h autosequencer - autosequencer control focus_start_time 5eh autosequencer - focus start time motor_start_time1 5fh autosequencer - motor start 1 time motor_start_time2 60h autosequencer - motor start 2 time radial_init_time 61h autosequencer - radial initialization time brake_time 62h autosequencer - brake time radcmdbyte 63h autosequencer - radial command byte osc_inc 68h focus/radial agc - agc control frequency of injected signal phase_shift 67h focus/radial agc - phase shift of injected signal level1 69h focus/radial agc - amplitude of signal injected level2 6ah focus/radial agc - amplitude of signal injected agc_gain 6ch focus/radial agc - focus/radial gain parameter ram address affects por value determines 1998 feb 26 43 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 8 limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. all v dd and v ss connections must be made externally to the same power supply. 2. equivalent to discharging a 100 pf capacitor via a 1.5 k w series resistor with a rise time of 15 ns. 3. equivalent to discharging a 200 pf capacitor via a 2.5 m h series inductor. 9 operating characteristics v dd = 3.0 to 3.6 v; v ss =0v; t amb = - 10 to +70 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage note 1 - 0.5 +6.5 v v i(max) maximum input voltage (any input) - 0.5 v dd + 0.5 v v o output voltage (any output) - 0.5 +6.5 v v dddiff difference between v dda and v ddd - 0.25 v i o output current (continuous) - 20 ma i ik dc input diode current (continuous) - 20 ma t amb operating ambient temperature - 10 +70 c t stg storage temperature - 55 +125 c v es electrostatic handling note 2 - 2000 +2000 v note 3 - 200 +200 v symbol parameter conditions min. typ. max. unit supply v dd supply voltage 3.0 3.3 3.6 v i dd supply current v dd =5v; n = 1 mode - 28 - ma decoder analog front-end (v dda = 3.3 v; v ssa =0v; t amb =25 c) c omparator inputs : hfin and hfref f clk clock frequency note 1 8 - 70 mhz v th(sw) switching voltage threshold 1.2 - v dd - 0.8 v v tpt hfin input voltage level - 1.0 - v r eference generator :i ref v iref reference voltage level (pin 18) - 0.5v dd - v 1998 feb 26 44 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 servo analog part (v dda = 3.3 v; v ssa =0v; t amb =25 c) p ins d1 to d4, r1, r2, v rh ,v rl and i reft i reft input reference current 1.935 - 5.45 m a r ireft external resistor on pin 10 220 - 620 k w v ireft voltage on reference current input - 1.2 - v i d(max) maximum input current for central diode input signal note 2 3.871 - 10.9 m a i r(max) maximum input current for satellite diode input signal note 2 1.935 - 5.45 m a v rl low level reference voltage 0 0 0 v v rh high level reference voltage output state 0; note 3 - 0.5 - v output state v; note 3 - 30% 0.5 10 v/44.4 +30% v output state 31; note 3 - 2.5 - v (thd+n)/s total harmonic distortion plus noise at 0 db; note 4 -- 50 - 45 db s/n signal-to-noise ratio - 55 - db psrr power supply rejection at v dda2 note 5 - 45 - db g tol gain tolerance note 6 - 12 0 +12 % d g v variation of gain between channels -- 2% a cs channel separation - 60 - d b digital inputs i nputs : reset, v1, v2, selpll (cmos input with pull - up resistor and hysteresis ) v thr(sw) switching voltage threshold rising -- 0.8v ddd v v thf(sw) switching voltage threshold falling 0.2v ddd -- v v hys hysteresis voltage - 0.33v ddd - v r i(pu) input pull-up resistance v i =0v - 50 - k w c i input capacitance -- 10 pf t resl reset pulse width (active low) reset only 1 --m s i nputs : scl, rab, sild and rck (cmos input ) v il low level input voltage - 0.3 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd + 0.3 v i li input leakage current v i =0 - v dd - 10 - +10 m a c in input capacitance -- 10 pf symbol parameter conditions min. typ. max. unit 1998 feb 26 45 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 digital outputs o utput : cl4 v ol low level output voltage i ol = +0.9 ma 0 - 0.4 v v oh high level output voltage i oh = - 0.9 ma v ddd - 0.4 - v ddd v c l load capacitance -- 25 pf t r output rise time c l =20pf; 0.8 to (v ddd - 0.8) -- 20 ns t f output fall time c l =20pf; (v ddd - 0.8) to 0.8 -- 20 ns o utput : cl16 v ol low level output voltage i ol =+1ma 0 - 0.4 v v oh high level output voltage i oh = - 1ma v ddd - 0.4 - v ddd v c l load capacitance -- 50 pf t r output rise time c l =20pf; 0.8 - (v ddd - 0.8) -- 15 ns t f output fall time c l =20pf; (v ddd - 0.8) - 0.8 -- 15 ns o utputs :v4 and v5 v ol low level output voltage i ol =+5ma 0 - 1.0 v v oh high level output voltage i oh = - 5ma v ddd - 1- v ddd v c l load capacitance -- 50 pf t r output rise time c l =20pf; 0.8 - (v ddd - 0.8) -- 10 ns t f output fall time c l =20pf; (v ddd - 0.8) - 0.8 -- 10 ns open-drain outputs o utputs : cflg, c2fail, status, kill, v3 and ldon ( open - drain output with protection diode to v dd ) v ol low level output voltage i ol = 0.9 ma 0 - 0.4 v i ol low level output current -- 2ma c l load capacitance -- 25 pf t f output fall time c l =20pf; (v ddd - 0.8) - 0.8 -- 30 ns symbol parameter conditions min. typ. max. unit 1998 feb 26 46 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 3-state outputs o utputs : ef, clk, wclk, data and cl11 v ol low level output voltage i ol = 1 ma 0 - 0.4 v v oh high level output voltage i oh = - 1ma v dd - 0.4 - v dd v c l load capacitance -- 50 pf t r output rise time c l =20pf; 0.8 - (v dd - 0.8) -- 15 ns t f output fall time c l =20pf; (v dd - 0.8) - 0.8 -- 15 ns i zo output 3-state leakage current v i =0 - v dd - 10 - +10 m a o utput : cl11 t h output high time (relative to clock period) v o =1.5v4550 55% o utputs : ra, fo, sl, sbsy, sfsy and sub v ol low level output voltage i ol = +0.9 ma 0 - 0.4 v v oh high level output voltage i oh = - 0.9 ma v dd - 0.4 - v dd v c l load capacitance -- 25 pf t r output rise time c l =20pf; 0.8 - (v dd - 0.8) -- 20 ns t f output fall time c l =20pf; (v dd - 0.8) - 0.8 -- 20 ns i zo 3-state leakage current v i =0 - v dd - 10 - +10 m a o utputs : moto1, moto2 and dobm v ol low level output voltage i ol =+5ma 0 - 1.0 v v oh high level output voltage i oh = - 5ma v dd - 1 - v dd v c l load capacitance -- 50 pf t r output rise time c l =20pf; 0.8 - (v dd - 0.8) -- 10 ns t f output fall time c l =20pf; (v dd - 0.8) - 0.8 -- 10 ns i zo 3-state leakage current v i =0 - v dd - 10 - +10 m a symbol parameter conditions min. typ. max. unit 1998 feb 26 47 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 notes 1. highest clock frequency at which data slicer produces 1010 output in analog self-test mode. 2. v rl = 0 v, f sys = 4.2336 mhz. the maximum input current depends on the value of the external resistor connected to i reft a) for d1 to d4: i max = 2.4/r ireft t 2.4/220 k w = 10.9 m a b) for r1 and r2:i max = 1.2/r ireft t 1.2/220 k w = 5.45 m a 3. internal reference source with 32 different output voltages. selection is achieved during a calibration period or via the serial interface. the values given are for an unloaded v rh . 4. v rh = 2.5 v and v rl = 0 v, measuring bandwidth: 200 hz to 20 khz, f i(adc) = 1 khz. 5. f ripple = 1 khz, v ripple = 0.5 v (p-p). 6. gain of the adc is defined as g adc =f sys /i max (counts/ m a); thus digital output = i i g adc where; a) digital output = the number of pulses at the digital output in counts/s and i i = the dc input current in m a. b) the maximum input current depends on the system frequency (f sys = 4.2336 mhz) and on v rh - v rl . c) the gain tolerance is the deviation from the calculated gain regarding note 2. 7. it is recommended that the series resistance of the crystal or ceramic resonator is 60 w . digital input/output i nput / output : sda [cmos input / open - drain i 2 c- bus output ( with protection diode to v ddd )] v il low level input voltage - 0.3 - 0.3v ddd v v ih high level input voltage 0.7v ddd - v ddd + 0.3 v i zo 3-state leakage current v i =0 - v ddd - 10 - +10 m a c in input capacitance -- 10 pf v ol low level output voltage i ol = 2 ma 0 - 0.4 v i ol low level output current -- 4ma c l load capacitance -- 50 pf t f output fall time c l =20pf; (v ddd - 0.8) - 0.8 -- 15 ns crystal oscillator i nput : crin ( external clock ) v il low level input voltage - 0.3 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd + 0.3 v i li input leakage current - 10 - +10 m a c in input capacitance -- 10 pf o utput : crout; see f igs 3 and 4 f xtal crystal frequency note 7 8 8.4672 35 mhz g m mutual conductance at 100khz - 10 - ma/v g v small signal voltage gain g v =g m r o - 18 - v/v c fb feedback capacitance -- 5pf c out output capacitance -- 10 pf symbol parameter conditions min. typ. max. unit 1998 feb 26 48 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 10 operating characteristics (subcode interface timing) v dd = 3.0 to 3.6 v; v ss =0v; t amb = - 10 to +70 c; unless otherwise speci?ed. note 1. the subcode timing is directly related to the overspeed factor n in normal operating mode. n is replaced by the disc speed factor d, in the lock-to-disc mode. symbol parameter conditions min. typ. max. unit subcode interface timing (single speed n); (see fig.31) ; note 1 i nput : rck t h input clock high time 2/n 4/n 6/n m s t l input clock low time 2/n 4/n 6/n m s t r input clock rise time -- 80/n ns t f input clock fall time -- 80/n ns t dc delay time sfsy to rck 10/n - 20/n m s o utputs : sbsy, sfsy and sub (c l =20pf) t bcy block cycle 12.0/n 13.3/n 14.7/n ms t bw sbsy pulse width -- 300/n m s t fcy frame cycle 122/n 136/n 150/n m s t fw sfsy pulse width (3-wire mode only) -- 366/n m s t fh sfsy high time -- 66/n m s t fl sfsy low time -- 84/n m s t dpac delay time sfsy to sub (p data) valid -- 1/n m s t dac delay time rck falling to sub -- 0 m s t hd hold time rck to sub -- 0.7/n m s 1998 feb 26 49 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 handbook, full pagewidth t w(sbsy) t w(sfsy) t r v dd ?0.8 v v dd ?0.8 v t sfsyl t sfsyh t cy(block) t cy(frame) t f t d(sfsy - rck) t d(sfsy - sub) t h(rck - sub) t d(rck - sub) sbsy sfsy rck sub sfsy (4-wire mode) sfsy (3-wire mode) 0.8 v 0.8 v 0.8 v mbg414 fig.31 subcode interface timing diagram. 1998 feb 26 50 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 11 operating characteristics (i 2 s-bus timing) v dd = 3.0 to 3.6 v; v ss =0v; t amb = - 10 to +70 c; unless otherwise speci?ed. note 1. the i 2 s-bus timing is directly related to the overspeed factor n in the normal operating mode. in the lock-to-disc mode n is replaced by the disc speed factor d. symbol parameter conditions min. typ. max. unit i 2 s timing (single speed n); (see fig.32) ; note 1 c lock output : sclk (cl = 20 pf) t cy output clock period sample rate = f s - 472.4/n - ns sample rate = 2f s - 236.2/n - ns sample rate = 4f s - 118.1/n - ns t ch clock high time sample rate = f s 166/n -- ns sample rate = 2f s 83/n -- ns sample rate = 4f s 42/n -- ns t cl clock low time sample rate = f s 166/n -- ns sample rate = 2f s 83/n -- ns sample rate = 4f s 42/n -- ns o utputs : wclk, data and ef (c l =20pf) t su set-up time sample rate = f s 95/n -- ns sample rate = 2f s 48/n -- ns sample rate = 4f s 24/n -- ns t h hold time sample rate = f s 95/n -- ns sample rate = 2f s 48/n -- ns sample rate = 4f s 24/n -- ns fig.32 i 2 s-bus timing diagram. dd v ?0.8 v 0.8 v dd v ?0.8 v 0.8 v t ch mbg407 t cl clock period t cy sclk wclk data ef t h t su 1998 feb 26 51 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 12 operating characteristics (microcontroller interface timing) v dd = 3.0 to 3.6 v; v ss =0v; t amb = - 10 to +70 c; unless otherwise speci?ed. symbol parameter conditions normal mode lock-to-disc mode unit min. max. min. max. microcontroller interface timing (4-wire bus mode; writing to registers 0 to f; reading q-channel subcode and decoder status); see figs 33 and 34; note 1 . i nputs scl and rab t cl input low time 480/n + 20 - 2400/n + 20 - ns t ch input high time 480/n + 20 - 2400/n + 20 - ns t r rise time - 480/n - 480/n ns t f fall time - 480/n - 480/n ns r ead mode (c l = 20 pf) t drd delay time rab to sda valid - 50 - 50 ns t pd propagation delay scl to sda 720/n - 20 960/n + 20 720/n + 20 4800/n + 20 ns t drz delay time rab to sda high-impedance - 50 - 50 ns w rite mode (c l = 20 pf) t sud set-up time sda to scl note 2 20 - 720/n - 20 - 720/n - ns t hd hold time scl to sda - 960/n + 20 - 4800/n + 20 ns t sucr set-up time scl to rab 240/n + 20 - 1200/n + 20 - ns t dwz delay time sda high-impedance to rab 0 - 0 - ns microcontroller interface timing (4-wire bus mode; servo commands); see figs 35 and 36 i nputs scl and sild t l input low time 710 - 710 - ns t h input high time 710 - 710 - ns t r rise time - 240 - 240 ns t f fall time - 240 - 240 ns 1998 feb 26 52 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 notes 1. the 4-wire bus mode microcontroller interface timing for writing to registers 0 to f, and reading q-channel subcode and decoder status, is a function of the overspeed factor n. in the lock-to-disc mode the maximum data rate is lower. 2. negative set-up time means that the data may change after clock transition. r ead mode (c l = 20 pf) t dld delay time sild to sda valid - 25 - 25 ns t pd propagation delay scl to sda - 950 - 950 ns t dlz delay time sild to sda high-impedance - 50 - 50 ns t sclr set-up time scl to sild 480 - 480 - ns t hclr hold time scl to sild 830 - 830 - ns w rite mode (c l = 20 pf) t sd set-up time sda to scl 0 - 0 - ns t hd hold time scl to sda 950 - 950 - ns t scl set-up time scl to sild 480 - 480 - ns t hcl hold time sild to scl 120 - 120 - ns t dplp delay between two sild pulses 70 - 70 -m s t dwz delay time sda high-impedance to sild 0 - 0 - ns symbol parameter conditions normal mode lock-to-disc mode unit min. max. min. max. 1998 feb 26 53 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 fig.33 4-wire bus microcontroller timing; read mode (q-channel subcode and decoder status information). sda (SAA7374) scl rab t r dd v ?0.8 v 0.8 v t r t f t f dd v ?0.8 v 0.8 v dd v ?0.8 v 0.8 v t pd t cl t ch t drd t drz high-impedance mbg660 fig.34 4-wire bus microcontroller timing; write mode (registers 0 to f). handbook, full pagewidth scl rab t r t f dd v ?0.8 v 0.8 v dd v ?0.8 v 0.8 v t hd t cl t ch t dwz mbg405 t r t f dd v ?0.8 v 0.8 v t cl t ch t sucr t sud sda (microcontroller) high-impedance 1998 feb 26 54 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 fig.35 4-wire bus microcontroller timing; read mode (servo commands). handbook, full pagewidth t dld t hclr t sclr t pd t dlz 0.8 v 0.8 v 0.8 v v dd ?0.8 v v dd ?0.8 v v dd ?0.8 v sild scl sda (SAA7374) mbg661 fig.36 4-wire bus microcontroller timing; write mode (servo commands). handbook, full pagewidth t dplp t l t scl t dwz t hcl t h t hd t sd t l 0.8 v 0.8 v 0.8 v v dd - 0.8 v v dd ?0.8 v v dd ?0.8 v sild scl sda (microcontroller) mbg416 1998 feb 26 55 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 13 application information handbook, full pagewidth 53 52 51 50 100 nf 100 nf 100 nf 100 nf 100 nf 49 64 63 62 61 60 59 58 57 56 55 54 28 29 30 31 32 17 18 19 20 21 22 23 24 25 26 27 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 7 6 3 1 4 5 2 9 (2) (3) ldon d2 d3 d4 d1 d5 d6 rfe 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tda1300 (1) SAA7374 to dobm transformer to power amplifiers 22 nf 2.2 w 150 k w v ssa1 v dda1 v dda v dd d1 d2 hfref ldon d3 v rl d4 r1 r2 i reft v rh v ssa2 selpll islice hfin v ssa3 v dda i ref v dda2 test1 crin crout test2 cl16 cl11 ra fo sl test3 v ddd1(p) dobm v ssd1 v2 v1 cflg c2fail v ddd3c status reset v ssd4 n.c. sild rab scl sda cl4 v ssd3 v ddd v ddd2(p) v ddd wclk sclk data ef kill v3 v4 v5 v ssd2 sub rck sfsy sbsy moto2 moto1 to dac to cd graphics 2.2 w 2.2 w 2.2 w 4.7 k w 4.7 k w 270 k w 22 k w 1 k w 100 nf microcontroller interface 33 m f 33 m f + v + v + v + v 220 pf 220 pf 47 pf 220 pf 220 pf 220 pf 220 pf 100 k w 100 k w 1 nf motor interface 100 nf mbg647 fig.37 typical application diagram. (1) for crystal oscillator circuit see figs 3 and 4. (2) for single and double-speed applications a 1 k w resistor should be used. for single-speed only applications a 2.2 k w resistor should be used. (3) the connections to tda1300 are shown for single foucault mechanisms. 1998 feb 26 56 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 14 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.10 2.75 2.55 0.25 0.45 0.30 0.23 0.13 14.1 13.9 0.8 17.45 16.95 1.2 0.8 7 0 o o 0.16 0.10 0.16 1.60 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.03 0.73 sot393-1 ms-022 96-05-21 97-08-04 d (1) (1) (1) 14.1 13.9 h d 17.45 16.95 e z 1.2 0.8 d e q e a 1 a l p detail x l (a ) 3 b 16 y c e h a 2 d z d a z e e v m a 1 64 49 48 33 32 17 x b p d h b p v m b w m w m 0 5 10 mm scale pin 1 index qfp64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm sot393-1 a max. 3.00 1998 feb 26 57 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 15 soldering 15.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 15.2 re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 15.3 wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 1998 feb 26 58 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 16 definitions 17 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 18 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. short-form speci?cation the data in this speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 1998 feb 26 59 philips semiconductors product speci?cation low voltage digital servo processor and compact disc decoder (cd7lv) SAA7374 notes internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1998 sca57 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 545102/00/02/pp60 date of release: 1998 feb 26 document order number: 9397 750 03143 |
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